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| Job #: | 456 |
| Job Title: | Multicore Imaging Software Platform Architect |
| Perm or Contract: | Permanent |
| Date Posted: | 24-Jan-2014 |
| Position: | SW Engineer |
| Location: | San Jose, CA |
| Area Code: | 408 |
| Skills: | OpenCL, MP programming, modeling, multicore, parallel computation, lead |
| Job Description: | Work with imaging system architects, marketing and customers on detailed architecture requirements, communications methods and libraries and development of specific applications (as products, demos or references examples) for especially for multi-core imaging/video applications Work with external partners and standards bodies on defining and refining MP programming models, tools, libraries, architectures in imaging/video and other computationally intensive embedded applications. The standards may include OpenVX, Renderscript and OpenCL and other parallel computation off-load standards. Work with core software development team on automating and generalizing methods developed in imaging to apply across problem domains and made available as core product features. Definition/evolution of requirements for memory/comms interface components (DMA, CBox, MP sync, queues) and development of suitable software demonstrations or productization of software elements to complement MP hardware features. Co-development of technical roadmaps for multi-core imaging and other vertical application platforms, especially in collaboration with senior technical management. Requirements: Substantial experience in development of new industry standards for multi-core image processing, especially OpenVX and OpenCL, including participation in standard setting bodies and implementation of programming environments and applications using those new standards in understanding and optimizing MP computation models, including message-passing and shared memory models , DMA-based, direct-sharing and cache-coherent data communication and efficient synchronization mechanisms in assessing available parallelism at the task, data and instruction level and doing code performance optimization or developing processor instruction set architecture or micro-architecture, especially DSP or media processing architectures that span the different levels of parallelism on definition, development, verification, packaging of software modules for MP applications, especially for high-performance synchronization, distribution of work and multi-core communication in algorithms or implementation of one or more data-intensive computation domains, including image, video, graphics, baseband signal processing and scientific computing. Experience in technical team leadership and coordination. |
| Job #: | 456 |